Static memory in computer organization
The CPU has direct access to RAM (Random Access Memory), which is a component of the computer's main memory. The CPU randomly accesses data and reads and writes into RAM. Due to its volatile nature, RAM loses its stored data whenever the power is interrupted. The currently processing data is stored in the RAM. Most of the data and programs that can be changed are stored in RAM.
Use software or system information tools like CPU-Z or HWiNFO to determine the type of RAM that is currently installed on your system. For supported RAM types, refer to the motherboard manual or the manufacturer's website for details.
The integrated RAM chips are of two types. They are:
1. Static RAM (SRAM).
2. Dynamic RAM (DRAM).
1. SRAM:
The circuits that makeup SRAM memories can retain the data stored for as long as power is available. It is clear from this that this type of memory requires continuing power. Cache memory is created utilizing SRAM memories.
SRAM Memory cells: Circuits used in static memory (SRAM) may maintain their state as long as power is present. Consequently, this kind of memory is referred to as volatile memory. SRAM's cell diagram may be seen in the graphic below. The illustration depicts the connection of two inverters to create a latch. T1 and T2 are two transistors that are utilized to connect the latch between two-bit lines. These transistors acts as switches that can be opened or closed in response to commands sent from the address decoder to the word line, which controls them. If the transistors are off, the information in the latch is retained while the word line is at 0 levels. No refresh period is needed for SRAM.
If the logic value at point A is 1 and at point B is 0. For example, the cell is in state 1. While the word line is inactive, this status is maintained.
![Static memory in computer organization](https://static.tutorialandexample.com/computer-fundamentals/static-memory-in-computer-organization1.png)
The address input to the address decoder initiates the word line's activation for the Read operation. Both the transistors (switches) T1 and T2 are closed by the active word line. Afterward, the bit values at sites A and B may be sent to their corresponding bit lines. The processor receives the sense/write circuit output at the end of the bit lines.
The word line is activated to close both switches during the Write operation by the address that the decoder receives. Afterward, the sense/write circuit supplies the bit value that is to be written into the cell, and the signals on the bit lines are then placed in the cell.
2. DRAM:
Electric charges are applied to capacitors in DRAM to store the binary data. The information that the capacitors store tends to deteriorate with time. Thus regular recharging is necessary to keep them functional. The DRAM requires refresh time. The main memory frequently consists of DRAM chips.
![Static memory in computer organization](https://static.tutorialandexample.com/computer-fundamentals/static-memory-in-computer-organization2.png)
DRAM Memory cells:
SRAM has a high cost since each cell needs several transistors, even though it is incredibly quick. DRAM is comparatively less costly than RAM since each cell in it has a transistor and a capacitor, as indicated in the diagram below, where C stands for the capacitor and T for the transistor. It is necessary to periodically recharge a DRAM cell since information is stored there as a charge on a capacitor.
Transistor T is switched on, and the bit line is given the proper voltage to store information in this cell. As a result, the capacitor stores a certain quantity of charge. Because of the capacitor's characteristics, the capacitor begins to discharge when the transistor is switched off. Therefore, the information recorded in the cell can only be read accurately if it is done before the capacitors' charge falls below a certain level.
Types of DRAMS:
There are different types of DRAM'S. They are:
1. Asynchronous DRAM:
Asynchronous DRAM is the sort of DRAM that was previously discussed. The memory device's time is asynchronously managed. A specialized memory controller circuit generates the timing control signals. The CPU must consider how long the memory takes to respond.
2. Synchronous DRAM:
The access speed of these RAM chips and the CPU's clock are in perfect time. The memory chips continue to be operational when the CPU anticipates them. Without imposing wait states, these memories function at the CPU-memory bus. Multiple SDRAM chips are combined into modules with the necessary capacity for the modules, which are commercially accessible.
3. Cache DRAM:
This memory is a unique sort of DRAM memory that includes an on-chip cache memory (SRAM) that serves as a high-speed buffer for the primary DRAM.